DS90UR124Q_14 Datasheet, PDF (2/36 Pages) Texas Instruments – MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset

DS90UR124Q, DS90UR241Q
SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013
Applications Diagram
Host
(Graphics/Video Processor, ECU)
Display
(Infotainment, Instrument Cluster, CID)
DE
RGB Data
Video
Source _Clock
HSYNC
DS90UR241
Serializer
VSYNC
(LVCMOS)
FPD-Link II
1 Pair
(LVDS)
DE
RGB Data
DS90UR124
Deserializer ^Clock
HSYNC
VSYNC
(LVCMOS)
LCD
Block Diagram
VODSEL
PRE
DEN
RAOFF
REN
www.ti.com
24
D_IN
TRFB
D_OUT+
D_OUT-
R_IN+
R_IN-
24
R_OUT
TCLK
PLL
TPWDNB
Timing
and
Control
SERIALIZER ± DS90UR241
RAOFF
RRFB
RPWDNB
BISTEN
BISTM
SLEW
PTOSEL
PLL
Timing
and
Control
LOCK
Clock
Recovery
DESERIALIZER ± DS90UR124
RCLK
PASS
2
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