DS90UB925Q-Q1 Datasheet, PDF (5/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
Pin Functions (continued)
PIN NAME
PIN #
I/O, TYPE
DESCRIPTION
DE
5
I, LVCMOS Data Enable Input Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
PCLK
10
I, LVCMOS Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6.
w/ pull down
I2S_CLK,
I2S_WC,
I2S_DA
13, 12, 11
I, LVCMOS
w/ pull down
Digital Audio Interface Data Input Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
OPTIONAL PARALLEL INTERFACE
I2S_DB
44
I, LVCMOS Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by
w/ pull down MODE_SEL pin or configuration register
Leave open if unused
I2S_DB can optionally be used as DIN17 or GPO_REG5.
GPIO[3:0]
36, 35, 26, 25
I/O, LVCMOS General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or
w/ pull down configuration register. See Table 6.
Leave open if unused.
Shared with DIN9, DIN8, DIN1 and DIN0
GPO_REG[ 13, 12, 11, 44, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6.
8:4]
43
w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or DIN17, DIN16.
CONTROL
PDB
21
I, LVCMOS Power-down Mode Input Pin
w/ pull-down PDB = H, device is enabled (normal operation)
Refer to Power Up Requirements and PDB Pin section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is
shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
I, Analog Device Configuration Select. See Table 4.
I²C
IDx
6
I, Analog I²C Serial Control Bus Device ID Address Select
External pull-up to V_DD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19.
SCL
8
I/O, LVCMOS I²C Clock Input / Output Interface
Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA
9
I/O, LVCMOS I²C Data Input / Output Interface
Open Drain Must have an external pull-up to V_DD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
STATUS
INTB
31
O, LVCMOS
Open Drain
FPD-LINK III SERIAL INTERFACE
Interrupt
INTB = H, normal
INTB = L, Interrupt request
Recommended pull-up: 4.7kΩ to V_DDIO
DOUT+
20
O, LVDS True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT-
19
O, LVDS Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF
23
Analog Common Mode Filter.
Connect 0.1µF to GND
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