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| DS90UB925Q-Q1 Datasheet, PDF (26/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel | |||
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DS90UB925Q-Q1
SNLS407D â APRIL 2012 â REVISED OCTOBER 2014
Programming (continued)
HOST
or
Salve SCL
SDA
VDD33
VDD33
R1
VR2
4.7k
4.7k
R2
IDx
SER
or
SCL DES
SDA
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To other
Devices
Figure 19. Serial Control Bus Connection
The configuration pin is the IDx pin. This pin sets one of 9 possible device addresses. A pull-up resistor and a
pull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 to
select one of the other 9 possible addresses. See Table 5.
#
IDEAL RATIO
VR2 / VDD33
1
0
2
0.121
3
0.152
4
0.180
5
0.208
6
0.303
7
0.345
8
0.389
9
0.727
Table 5. Serial Control Bus Addresses for IDx
IDEAL VR2
(V)
0
0.399
0.502
0.594
0.685
0.999
1.137
1.284
2.399
SUGGESTED
RESISTOR
R1 k⦠(1% tol)
Open
294
280
137
118
115
102
115
90.9
SUGGESTED
RESISTOR
R2 k⦠(1% tol)
40.2 or Any
40.2
49.9
30.1
30.9
49.9
53.6
73.2
243
ADDRESS 7'b
0x0C
0x0D
0x0E
0x0F
0x10
0x13
0x14
0x15
0x1B
ADDRESS 8'b
APPENDED
0x18
0x1A
0x1C
0x1E
0x20
0x26
0x28
0x2A
0x36
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 20.
SDA
SCL
S
START condition, or
START repeat condition
Figure 20. Start and Stop Conditions
P
STOP condition
26
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Product Folder Links: DS90UB925Q-Q1
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