DS90UB925Q-Q1 Datasheet, PDF (13/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
t_DJIT
t_DJIT
VOD (+)
DOUT
(Diff.)
EYE OPENING
0V
VOD (-)
t_BIT (1 UI)
Figure 7. Serializer CML Output Jitter
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_SP
t_r
t_BUF
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
STOP START
Figure 8. Serial Control Bus Timing Diagram
6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_LHT
CML Output Low-to-High
Transition Time
t_HLT
CML Output High-to-Low
Transition Time
See Figure 4
t_DIS
Data Input Setup to PCLK
See Figure 5
t_DIH
Data Input Hold from PCLK
t_PLD
Serializer PLL Lock Time
t_SD
Delay — Latency
Output Total Jitter,
t_TJIT
Bit Error Rate ≥10^-10
Figure 7 ^{(2) (3) (4)}
See Figure 6 ⁽¹⁾
R_L = 100Ω
f = 45MHz
PIN/FREQ.
DOUT+,
DOUT-
R[7:0],
G[7:0],
B[7:0], HS,
VS, DE,
PCLK,
I2S_CLK,
I2S_WC,
I2S_DA
f = 15 -
45MHz
f = 15 -
45MHz
DOUT+,
DOUT-
MIN TYP
80
80
2.0
MAX UNIT
130 ps
130 ps
ns
2.0
ns
131*T
145*T
0.25
ns
ns
0.30 UI
(1) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by characterization and is not tested in production.
(3) Specification is ensured by design and is not tested in production.
(4) UI – Unit Interval is equivalent to one serialized data bit width 1UI = 1 / (35*PCLK). The UI scales with PCLK frequency.
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