DS90UB925Q-Q1 Datasheet, PDF (40/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
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8.2.2 Detailed Design Procedure
Figure 23 shows a typical application of the DS90UB925Q-Q1 serializer for an 85 MHz 24-bit Color Display
Application. The camera application has the same recommended connections. The CML outputs must have an
external 0.1 μF AC coupling capacitor on the high speed serial lines. The serializer has an internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors and two (2)
additional 1μF capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2)
VDDs (V_DD33 and V_DDIO) for effective noise suppression. The interface to the graphics source is with 3.3V
LVCMOS levels, thus the V_DDIO pin is connected to the 3.3 V rail. A RC delay is placed on the PDB signal to
delay the enabling of the device until power is stable.
8.2.3 Application Curves
Time (100 ps/DIV)
Figure 26. Serializer Eye Diagram with 78 MHz TX Pixel
Clock
Time (2.5 ns/DIV)
Figure 27. Serializer CML Output with 78 MHz TX Pixel
Clock
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