DS90UB925Q-Q1 Datasheet, PDF (29/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
Register Maps (continued)
ADD
(dec)
4
5
ADD
(hex)
0x04
0x05
REGISTER
NAME
Configuration
[1]
I2C Control
Table 6. Serial Control Bus Registers (continued)
BIT(S)
7
6
5
4
3
2
1
0
7:5
4:3
2
1
0
REGIST
ER
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x80
0x00
Failsafe
State
Input Failsafe State
1: Failsafe to Low
0: Failsafe to High
Reserved
CRC Error
Reset
Clear back channel CRC Error Counters
This bit is NOT self-clearing
1: Clear Counters
0: Normal Operation
RGB
DE Gate
1: Gate RGB data with DE in Backward Compatibility
mode and with Non-HDCP Deserializer
0: Pass RGB data independent of DE in Backward
Compatibility mode and Non-HDCP operation (default)
Backward
Compatible
select by
pin or
register
control
Backward Compatible (BC) mode set by MODE_SEL
pin or register
1: BC is set by register bit. Use register bit reg_0x04[2]
to set BC Mode
0: BC is set by MODE_SEL pin.
Backward
Compatible
Mode
Select
Backward compatible (BC) mode to DS90UR906Q or
DS90UR908Q, if reg_0x04[3] = 1
1: Backward compatible with DS90UR906Q or
DS90UR908Q
0: Backward Compatible is OFF (default)
LFMODE
select by
pin or
register
control
Frequency range is set by MODE_SEL pin or register
1: Frequency range is set by register. Use register bit
reg_0x04[0] to set LFMODE
0: Frequency range is set by MODE_SEL pin.
LFMODE
Frequency range select
1: PCLK range = 5MHz - <15 MHz), if reg_0x04[1] = 1
0: PCLK range = 15MHz - 85MHz (default)
Reserved
SDA Output SDA output delay
Delay
Configures output delay on the SDA output. Setting this
value will increase output delay in units of 40ns.
Nominal output delay values for SCL to SDA are
00: 240ns
01: 280ns
10: 320ns
11: 360ns
Local Write
Disable
Disable remote writes to local registers
Setting the bit to a 1 prevents remote writes to local
device registers from across the control channel. It
prevents writes to the Serializer registers from an I2C
master attached to the Deserializer.
Setting this bit does not affect remote access to I2C
slaves at the Serializer
I2C Bus
Timer
Speedup
Speed up I2C bus watchdog timer
1: Watchdog timer expires after ~50 ms.
0: Watchdog Timer expires after ~1 s
I2C Bus
timer
Disable
Disable I2C bus watchdog timer
When the I2C watchdog timer may be used to detect
when the I2C bus is free or hung up following an invalid
termination of a transaction.
If SDA is high and no signalling occurs for ~1 s, the I2C
bus assumes to be free. If SDA is low and no signaling
occurs, the device attempts to clear the bus by driving
9 clocks on SCL
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