DS90UB925Q-Q1 Datasheet, PDF (39/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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Typical Application (continued)
DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
HOST
Graphics
Processor
V_DDIO V_DD33
(1.8V or 3.3V) (3.3V)
V_DD33 V_DDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO ³
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT-
DS90UB925Q-Q1
Serializer
DAP
100: STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UB926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
RGB Display
720p
24-bit color depth
3 _{I2S AUDIO}
(STEREO)
MCLK
DAP
720p
Megapixel
Image
Sensor
Figure 24. Typical Display System Diagram
V_DDIO
V_DD33
(1.8V or 3.3V) (3.3V)
V_DD33
V_DDIO
(3.3V) (1.8V or 3.3V)
D[0:n]
HS
VS
PCLK
GPIO
PDB
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair/AC Coupled
0.1 PF
0.1 PF
DOUT-
DS90UB925Q-Q1
Serializer
DAP
100: STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UB926Q-Q1
Deserializer
DAP
ROUT[0:n]
HS
VS
PCLK
GPIO
LOCK
PASS
Image
Processor
Unit
Figure 25. Typical Camera Applications Diagram
8.2.1 Design Requirements
For the typical design application, use the following as input parameters.
Table 7. Design Parameters
DESIGN PARAMETER
VDDIO
VDD33
AC Coupling Capacitor for DOUT±
PCLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
3.3 V
100 nF
85 MHz
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