DS90UB925Q-Q1 Datasheet, PDF (18/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
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Feature Description (continued)
7.3.11 Serial Link Fault Detect
The serial link fault detection is able to detect any of following seven (7) conditions:
1. cable open
2. “+” to “-“ short
3. “+” short to GND
4. “-“ short to GND
5. “+” short to battery
6. “-“ short to battery
7. Cable is linked correctly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address
0x0C Table 6.
7.3.12 Pixel Clock Edge Select (RFB)
The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines
the edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB
is LOW (‘0’), data is latched on the Falling edge of the PCLK.
7.3.13 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequency
of the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is
High, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,
a PDB reset is required.
7.3.14 Interrupt Pin — Functional Description And Usage (INTB)
1. On DS90UB925, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UB926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UB925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an
interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read ISR register .
5. A read to ISR will clear the interrupt at the DS90UB925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving INTB_IN. This would be when the downstream device releases the
INTB_IN (pin 16) on the DS90UB926Q-Q1. The system is now ready to return to step (1) at next falling edge
of INTB_IN.
7.3.15 Internal Pattern Generation
The DS90UB925Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing and
debugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple and
repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down
mode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the test
pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application
Note AN-2198 (SNLA132).
7.3.16 GPIO[3:0] and GPO_REG[8:4]
In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UB925Q-Q1 can be used as the
general purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.
7.3.16.1 GPIO[3:0] Enable Sequence
See Table 1 for the GPIO enable sequencing.
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