DS90UB925Q-Q1 Datasheet, PDF (28/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
www.ti.com
Register Maps (continued)
ADD
(dec)
3
ADD
(hex)
0x03
REGISTER
NAME
Configuration
[0]
Table 6. Serial Control Bus Registers (continued)
BIT(S)
7
6
5
4
3
2
1
0
REGIST
ER
TYPE
RW
RW
RW
RW
RW
RW
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0xD2
Back
channel
CRC
Checker
Enable
Back Channel Check Enable
1: Enable
0: Disable
Reserved
I2C Remote Automatically Acknowledge I2C Remote Write When
Write Auto enabled, I2C writes to the Deserializer (or any remote
Acknowledg I2C Slave, if I2C PASS ALL is enabled) are
e
immediately acknowledged without waiting for the
Deserializer to acknowledge the write. This allows
higher throughput on the I2C bus
1: Enable
0: Disable
Filter
Enable
HS, VS, DE two clock filter When enabled, pulses less
than two full PCLK cycles on the DE, HS, and VS
inputs will be rejected
1: Filtering enable
0: Filtering disable
I2C Pass-
through
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
Reserved
PCLK Auto Switch over to internal OSC in the absence of PCLK
1: Enable auto-switch
0: Disable auto-switch
TRFB
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling
Clock Edge.
28
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