DS90UB925Q-Q1 Datasheet, PDF (4/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
5 Pin Configuration and Functions
DS90UB925Q-Q1
48 Pin WQFN
Top View
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G2 / DIN10 37
G3 / DIN11 38
G4 / DIN12 39
G5 / DIN13 40
G6 / DIN14 41
G7 / DIN15 42
GPO_REG4 / B0 / DIN16 43
I2S_DB / GPO_REG5 / B1 / DIN17 44
B2 / DIN18 45
B3 / DIN19 46
B4 / DIN20 47
B5 / DIN21 48
DS90UB925Q-Q1
TOP VIEW
DAP = GND
24 MODE_SEL
23 CMF
22 VDD33
21 PDB
20 DOUT+
19 DOUT-
18 RES1
17 CAPHS12
16 NC
15 RES0
14 CAPP12
13 I2S_CLK / GPO_REG8
Pin Functions
PIN NAME
PIN #
I/O, TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
DIN[23:0] /
R[7:0],
G[7:0],
B[7:0]
25, 26, 27, 28,
29, 32, 33, 34,
35, 36, 37, 38,
39, 40, 41, 42,
43, 44, 45, 46,
47, 48, 1, 2
I, LVCMOS
w/ pull down
Parallel Interface Data Input Pins
Leave open if unused
DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1
DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3
DIN16 / B0 can optionally be used as GPIO4 and DIN17 / B1 can optionally be used as
GPIO5
HS
3
I, LVCMOS Horizontal Sync Input Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when
the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Table 6.
VS
4
I, LVCMOS Vertical Sync Input Pin
w/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
4
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