DS90UB925Q-Q1 Datasheet, PDF (34/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
www.ti.com
Register Maps (continued)
ADD
(dec)
20
22
23
24
25
27
ADD
(hex)
0x14
0x16
0x17
0x18
0x19
0x1B
Table 6. Serial Control Bus Registers (continued)
REGISTER
NAME
Oscillator Clock
Source and
BIST Status
BCC Watchdog
Control
I2C Control
SCL High Time
SCL Low Time
BIST BC Error
BIT(S)
7:3
2:1
0
7:1
0
7
6
5:4
3:0
7:0
7:0
7:0
REGIST
ER
TYPE
RW
R
RW
RW
RW
RW
RW
RW
RW
R
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x00
0xFE
0x5E
0xA1
0xA5
0x00
Reserved
OSC Clock
Source
OSC Clock Source
(When LFMODE = 1, Oscillator = 12.5MHz ONLY)
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
BIST
Enable
Status
BIST status
1: Enabled
0: Disabled
Timer Value The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time.
This field sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2 ms.
This field should not be set to 0
Timer
Control
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
I2C Pass
All
I2C Control
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C Slave IDs that do not match the
Serializer I2C Slave ID.
0: Enable Forward Control Channel pass-through only
of I2C accesses to I2C Slave IDs matching either the
remote Deserializer Slave ID or the remote Slave ID.
Reserved
SDA Hold
Time
Internal SDA Hold Time
Configures the amount of internal hold time provided
for the SDA input relative to the SCL input. Units are 40
ns
I2C Filter
Depth
Configures the maximum width of glitch pulses on the
SCL and SDA inputs that will be rejected. Units are 5
ns
SCL HIGH
Time
I2C Master SCL High Time
This field configures the high pulse width of the SCL
output when the Serializer is the Master on the local
I2C bus. Units are 40 ns for the nominal oscillator clock
frequency. The default value is set to provide a
minimum 5us SCL high time with the internal oscillator
clock running at 32.5MHz rather than the nominal
25MHz.
SCL LOW
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the Serializer is the Master on the local
I2C bus. This value is also used as the SDA setup time
by the I2C Slave for providing data prior to releasing
SCL during accesses over the Bidirectional Control
Channel. Units are 40 ns for the nominal oscillator
clock frequency. The default value is set to provide a
minimum 5us SCL low time with the internal oscillator
clock running at 32.5MHz rather than the nominal
25MHz.
BIST Back
Channel
CRC Error
Counter
BIST Mode Back Channel CRC Error Counter
This error counter is active only in the BIST mode. It
clears itself at the start of the BIST run.
34
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