DS90UB925Q-Q1 Datasheet, PDF (1/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
DS90UB925Q-Q1 5 to 85 MHz 24-Bit Color FPD-Link III Serializer
With Bidirectional Control Channel
1 Features
•1 Bidirectional Control Interface Channel Interface
with I²C Compatible Serial Control Bus
• Supports High Definition (720 p) Digital Video
Format
• RGB888 + VS, HS, DE and I2S Audio Supported
• Supports Two 10–bit Camera Video Streams
• 5 – 85MHz PCLK Supported
• Single 3.3 V Operation with 1.8 V or 3.3 V
Compatible LVCMOS I/O Interface
• AC-Coupled STP Interconnect Up to 10 Meters
• Parallel LVCMOS Video Inputs
• DC-Balanced and Scrambled Data with
Embedded Clock
• Supports Repeater Application
• Internal Pattern Generation
• Low Power Modes Minimize Power Dissipation
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
• >8kV HBM and ISO 10605 ESD Rating
• Backward Compatible to FPD-Link II
2 Applications
• Automotive Display for Navigation
• Rear Seat Entertainment Systems
• Automotive Driver Assistance
• Automotive Megapixel Camera Systems
3 Description
The DS90UB925Q-Q1 serializer, in conjunction with
the DS90UB926Q-Q1 deserializer, provides a
complete digital interface for concurrent transmission
of high-speed video, audio, and control data for
automotive display and image sensing applications.
The chipset is ideally suited for automotive video-
display systems with HD formats and automotive
vision systems with megapixel resolutions. The
DS90UB925Q-Q1 incorporates an embedded
bidirectional control channel and low latency GPIO
controls. This chipset translates a parallel interface
into a single pair high-speed serialized interface. The
serial bus scheme, FPD-Link III, supports full duplex
of high-speed video data transmission and
bidirectional control communication over a single
differential link. Consolidation of video data and
control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
The DS90UB925Q-Q1 serializer embeds the clock,
DC scrambles & balances the data payload, and level
shifts the signals to high-speed low voltage
differential signaling. Up to 24 data bits are serialized
along the video control signals.
Serial transmission is optimized by a user selectable
de-emphasis. EMI is minimized by the use of low
voltage differential signaling, data scrambling and
randomization and spread spectrum clocking
compatibility.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UB925Q-Q1 WQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HOST
Graphics
Processor
VDDIO V_DD33
(1.8V or 3.3V) (3.3V)
VDD33 VDDIO
(3.3V) (1.8V or 3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
PDB
I2S AUDIO ³
(STEREO)
SCL
SDA
IDx
DOUT+
FPD-Link III
1 Pair / AC Coupled
0.1 PF
0.1 PF
DOUT-
DS90UB925Q-Q1
Serializer
DAP
100: STP Cable
PDB
OSS_SEL
OEN
MODE_SEL MODE_SEL
INTB
INTB_IN
SCL
SDA
IDx
RIN+
RIN-
DS90UB926Q-Q1
Deserializer
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
LOCK
PASS
RGB Display
720p
24-bit color depth
3
I2S AUDIO
(STEREO)
MCLK
DAP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.