DS90UB925Q-Q1 Datasheet, PDF (19/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
Feature Description (continued)
Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UB925Q-Q1, then write 0x05 to
address 0x1F on DS90UB926Q-Q1.
#
DESCRIPTION
1
Enable 18-bit
mode
2
GPIO3
3
GPIO2
4
GPIO1
5
GPIO0
Table 1. GPIO Enable Sequencing Table
DEVICE
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
DS90UB925Q-Q1
DS90UB926Q-Q1
FORWARD CHANNEL
0x12 = 0x04
Auto Load from DS90UB925Q-Q1
0x0F = 0x03
0x1F = 0x05
0x0E = 0x30
0x1E = 0x50
0x0E = 0x03
0x1E = 0x05
0x0D = 0x93
0x1D = 0x95
BACK CHANNEL
0x12 = 0x04
Auto Load from DS90UB925Q-Q1
0x0F = 0x05
0x1F = 0x03
0x0E = 0x50
0x1E = 0x30
0x0E = 0x05
0x1E = 0x03
0x0D = 0x95
0x1D = 0x93
7.3.16.2 GPO_REG[8:4] Enable Sequence
GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 2
for the GPO_REG enable sequencing.
Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UB925Q-Q1 only.
DS90UB926Q-Q1 is automatically configured as in the 18-bit mode.
Step 2: To enable GPO_REG8 outputs an “1”, write 0x90 to address 0x11 on DS90UB925Q.
#
DESCRIPTION
1
Enable 18-bit mode
2
GPO_REG8
3
GPO_REG7
4
GPO_REG6
5
GPO_REG5
6
GPO_REG4
Table 2. GPO_REG Enable Sequencing Table
DEVICE
DS90UB925Q-Q1
DS90UB925Q-Q1
DS90UB925Q-Q1
DS90UB925Q-Q1
DS90UB925Q-Q1
DS90UB925Q-Q1
LOCAL ACCESS
0x12 = 0x04
0x11 = 0x90
0x11 = 0x10
0x11 = 0x09
0x11 = 0x01
0x10 = 0x90
0x10 = 0x10
0x10 = 0x09
0x10 = 0x01
0x0F = 0x90
0x0F = 0x10
LOCAL OUTPUT
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
7.3.17 I2S Transmitting
In normal 24-bit RGB operation mode, the DS90UB925Q-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WC
and I2S_DA. The optionally packetized audio information can be transmitted during the video blanking (data
island transport) or during active video (forward channel frame transport). Note: The bit rates of any I2S bits must
maintain one fourth of the PCLK rate.
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