DS90UB925Q-Q1 Datasheet, PDF (17/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

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Feature Description (continued)
DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
PCLK
IN
HS/VS/DE
IN
Latency
PCLK
OUT
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 12. Video Control Signal Filter Waveform
7.3.6 EMI Reduction Features
7.3.6.1 Input SSC Tolerance (SSCT)
The DS90UB925Q-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile
up to ±2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.
7.3.7 LVCMOS V_DDIO Option
1.8 V or 3.3 V Inputs and Outputs are powered from a separate V_DDIO supply to offer compatibility with external
system interface signals.
NOTE
When configuring the V_DDIO power supplies, all the single-ended data and control input
pins for device need to scale together with the same operating V_DDIO levels.
7.3.8 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the
host or through the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display
is not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO
have reached final levels; no external components are required. In the case of driven by the V_DDIO = 3.0V to 3.6V
or V_DD33 directly, a 10 kohm resistor to the V_DDIO = 3.0V to 3.6V or V_DD33 , and a >10uF capacitor to the ground
are required (See Figure 23).
7.3.9 Remote Auto Power Down Mode
The Serializer features a remote auto power down mode. During the power down mode of the pairing
deserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of the
Serializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal power
on mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.
7.3.10 Input PCLK Loss Detect
The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A
clock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again,
the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registers
values are still RETAINED.
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