DS90UB925Q-Q1 Datasheet, PDF (36/51 Pages) Texas Instruments – 5 to 85 MHz 24-Bit Color FPD-Link III Serializer With Bidirectional Control Channel

DS90UB925Q-Q1
SNLS407D – APRIL 2012 – REVISED OCTOBER 2014
www.ti.com
Register Maps (continued)
ADD
(dec)
101
102
103
198
199
ADD
(hex)
0x65
0x66
0x67
0xC6
0xC7
Table 6. Serial Control Bus Registers (continued)
REGISTER
NAME
Pattern
Generator
Configuration
BIT(S)
7:5
4
3
2
1
0
Pattern
7:0
Generator
Indirect Address
Pattern
7:0
Generator
Indirect Data
ICR
7:6
5
4:1
0
ISR
7:6
5
4:1
0
REGIST
ER
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
DEFAULT
(hex)
FUNCTION
DESCRIPTION
0x00
0x00
0x00
Reserved
Pattern
Generator
18 Bits
18-bit Mode Select
1: Enable 18-bit color pattern generation. Scaled
patterns will have 64 levels of brightness and the R, G,
and B outputs use the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns
use 256 levels of brightness.
Pattern
Generator
External
Clock
Select External Clock Source
1: Selects the external pixel clock when using internal
timing.
0: Selects the internal divided clock when using internal
timing
This bit has no effect in external timing mode
(PATGEN_TSEL = 0).
Pattern
Generator
Timing
Select
Timing Select Control
1: The Pattern Generator creates its own video timing
as configured in the Pattern Generator Total Frame
Size, Active Frame Size. Horizontal Sync Width,
Vertical Sync Width, Horizontal Back Porch, Vertical
Back Porch, and Sync Configuration registers.
0: the Pattern Generator uses external video timing
from the pixel clock, Data Enable, Horizontal Sync, and
Vertical Sync signals.
Pattern
Enable Inverted Color Patterns
Generator 1: Invert the color output.
Color Invert 0: Do not invert the color output.
Pattern
Generator
Auto-Scroll
Enable
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the
next enabled pattern after the number of frames
specified in the Pattern Generator Frame Time (PGFT)
register.
0: The Pattern Generator retains the current pattern.
Indirect
Address
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to
reading or writing the Pattern Generator Indirect Data
register.
See AN-2198 (SNLA132).
Indirect
Data
When writing to indirect registers, this register contains
the data to be written. When reading from indirect
registers, this register contains the read back value.
See AN-2198 (SNLA132)
Reserved
IS_RX_INT
Interrupt on Receiver interrupt
Enables interrupt on indication from the Receiver.
Allows propagation of interrupts from downstream
devices
Reserved
INT Enable Global Interrupt Enable
Enables interrupt on the interrupt signal to the
controller.
Reserved
IS RX INT
Interrupt on Receiver interrupt
Receiver has indicated an interrupt request from down-
stream device
Reserved
INT
Global Interrupt
Set if any enabled interrupt is indicated
36
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