CDCE62002 Datasheet, PDF (7/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
COMPUTING THE OUTPUT FREQUENCY
Figure 7 presents the block diagram of the CDCE62002 synthesizer highlighting the clock path for a single
output. It also identifies the following regions containing dividers comprising the complete clock path:
• R: Is the Reference divider values.
• O: The output divider value (see Output Block for more details)
• I: The input divider value (see Synthesizer Block for more details)
• P: The Prescaler divider value (see Synthesizer Block of more details)
• F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for
more details)
R
Reference
Divider
Fin
EXT_LFP
EXT_LFN
I
Input
Divider
Feedback
Divider
F
PFD /
CP
P
Prescaler
O
Output
Divider 0
Output
Divider 1
U0P
F _OUT
U0N
U1P
U1N
Figure 7. CDCE62002 Clock Path – Synthesizer
With respect to Figure 7, any output frequency generated by the CDCE62002 relates to the input frequency
connected to the Synthesizer Block by the following equation:
F
F_OUT = F_IN × _{R ×I × O}
(1)
Equation 1 holds true subject to the following constraints:
1.750GHz < O ×P ×F_OUT < 2.356GHz
(2)
And the comparison frequency F_COMP,
40.0 kHz ≤ F_COMP ≤ 40 MHz
Where:
F_COMP
=
F_IN
R ×I
(3)
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE62002
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