CDCE62002 Datasheet, PDF (3/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
DEVICE INFORMATION
PIN FUNCTIONS
Table 1. CDCE62002 Pin Functions⁽¹⁾
NAME
VCC_OUT0
VCC_OUT1
PIN
QFN
9,12 13,16
VCC_PLLDIV
VCC_PLLD
VCC_PLLA
VCC_VCO
VCC_IN
VCC_AUX
GND_PLLDIV
GND
SPI_MISO
22
4
28
24
31
1
21
PAD
7
SPI_LE
18
SPI_CLK
17
SPI_MOSI
8
PD
6
AUX_IN
2
REF+
REF–
PLL_LOCK
TESTSYNC
REG_CAP1
REG_CAP2
REG_CAP3
REG_CAP4
VBB
EXT_LFP
EXT_LFN
U0P:U0N
U1P:U1N
29
30
32
19
5
27
20
23
3
25
26
11,10 15,14
TYPE
DESCRIPTION
Power
Power
Power
A. Power
A. Power
Power
A. Power
Ground
Ground
OD
I
I
I
I
I
I
I
O
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
O
3.3V Supply for the Output Buffers.
There is no internal connection between V_CC and AV_CC. It is recommended, that each V_CC
uses its own supply filter.
3.3V Supply Power for the PLL circuitry.
3.3V Supply Power for the PLL circuitry.
3.3V Supply Power for the PLL circuitry.
3.3V Supply Power for the VCO Circuitry.
3.3V Supply Power for Input Buffer Circuitry
3.3V Supply Power for Crystal/Auxiliary Input Buffer Circuitry
Ground for PLL Divider circuitry. (short to GND)
Ground is on Thermal PAD. See Layout recommendation
3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data
Output to the SPI bus interface.
LVCMOS input, control Latch Enable for Serial Programmable Interface.
Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on the
Rising edge of PD. The input has an internal 150-kΩ pull-up resistor
LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis.
LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for the
SPI bus interface.
PD or Power Down Pin is an active low pin and can be activated externally or via the
corresponding Bit in SPI Register 2
In case of PD is asserted , the Device shuts Down and after PD goes high the EEPROM
Loads into RAM and the VCO core re-starts calibration, PLL will try to relock and the
Output dividers will get re-initiated. The LVPECL outputs are static low and high
respectively and the LVCMOS outputs are all low or high if inverted. The input has an
internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into
RAM on the Rising edge of PD.
Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry. This
input can also be driven by an LVCMOS signal.
This input also serves as the External Feedback Input that feeds directly to the PFD.
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock.
Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. In case of
LVCMOS signaling pull-down this pin.
PLL Lock indicator
Test Point for Use for TI Internal SYNC Testing.
Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)
Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)
Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)
Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)
Capacitor for the internal termination Voltage. Connect to a 1 µF Capacitor (Y5V)
External Loop Filter Input Positive
External Loop Filter Input Negative.
The Main outputs of CDCE62002 are user definable and can be any combination of up to
2 LVPECL outputs, 2 LVDS outputs or up to 4 LVCMOS outputs. The outputs are
selectable via SPI interface. The power-up setting is EEPROM configurable.
(1) NOTE: All VCC pins need to be connected for the device to operate properly.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE62002
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