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CDCE62002 Datasheet, PDF (5/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
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CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
Interface and Control Block
The CDCE62002 is a highly flexible and configurable architecture and as such contains a number of registers so
that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM
determine device configuration at all times. On power-up, the CDCE62002 copies the contents of the EEPROM
into the RAM and the device begins operation based on the default configuration stored in the EEPROM.
Systems that do not have a host system to communicate with the CDCE62002 use this method for device
configuration. The CDCE62002 provides the ability to lock the EEPROM; enabling the designer to implement a
fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial
Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62002 during system
operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is
unlocked.
PD
SPI_ LE
SPI_ CLK
SPI_ MOSI
SPI_ MISO
Interface
&
Control
Static RAM Device Registers
Register 2
Register 1
Register 0
EEPROM Device Registers
Register 2
Register 1
Register 0
Figure 3. CDCE62002 Interface and Control Block
Device
Hardware
Input Block
The Input Block includes one Universal Input Buffer and an Auxiliary Input. The Input Block buffers the incoming
signals and facilitates signal routing to the Internal Synthesizer Block via the smart multiplexer (called the Smart
MUX). The CDCE62002 can divide the REF_IN signal via the dividers present on the inputs of the first stage of
the Smart MUX.
Smart MUX
Control
LVPECL/LVDS 500 MHz
LVCMOS 250 MHz
REF_IN
Reference Divider
/1 - /8
Synthesizer
Reference
Crystal : 2 MHz – 42 MHz
XTAL/
Single Ended : 2 MHz - 75 MHz AUX_IN
Figure 4. CDCE62002 Input Block
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE62002
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