CDCE62002 Datasheet, PDF (20/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
CDCE62002 SPI Command Structure
The CDCE62002 supports four commands issued by the Master via the SPI:
• Write to RAM
• Read Command
• Copy RAM to EEPROM – unlock
• Copy RAM to EEPROM – lock
Table 6 provides a summary of the CDCE62002 SPI command structure. The host (master) constructs a Write to
RAM command by specifying the appropriate register address in the address field and appends this value to the
beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The
host must issue a Read Command to initiate a data transfer from the CDCE62002 back to the host. This
command specifies the address of the register of interest in the data field.
Table 6. CDCE62002 SPI Command Structure
Register Operation
0
Write to RAM
1
Write to RAM
2
Status/Control
Instruction Read Command
Instruction RAM EEPROM
Instruction RAM EEPROM
Data Field (28 Bits)
Addr Field
(4 BIts)
222222221111111111
NVM 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 3 2 1 0
Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0
Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 1
No X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 0
No 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A 1 1 1 0
Unlock 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Lock ⁽¹⁾ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1
(1) CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can
only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed.
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