CDCE62002 Datasheet, PDF (28/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
INPUT BLOCK
The Input Block includes one Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer.
Register 0
23
Universal Input Buffers
LVPECL : 500 MHz
LVDS: 500 MHz
LVCMOS : 250 MHz
REF_IN
Auxiliary Input
Crystal : 2 MHz – 42 MHz
XTAL /
Single Ended : 2 MHz - 75 MHz AUX_IN
Register 0
01
Smart MUX
Control
Smart Multiplexer
Pre-Divider
/1 or /2
Reference Divider
/1 - /8
9
87 6
Register 0
Figure 21. CDCE62002 Input Block With References to Registers
Smart
MUX
The CDCE62002 provides a Reference Divider that divides the clock exiting Reference (REF_IN) input buffer.
Table 12. CDCE62002 Reference Divider Settings
BIT NAME →
REGISTER BIT →
REFDIVIDE3
0.9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
REFERENCE DIVIDER
REFDIVIDE2 REFDIVIDE1
0.8
0.7
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
REFDIVIDE0
0.6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TOTAL
DIVIDE
RATIO
/1
/2
/3
/4
/5
/6
/7
/8
/2
/4
/6
/8
/10
/12
/14
/16
28
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