CDCE62002 Datasheet, PDF (6/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
Synthesizer Block
Figure 5 presents a high-level overview of the Synthesizer Block on the CDCE62002. This block contains the
Phase lock loop, internal loop filter and dual Voltage controlled oscillators. Only one VCO is selected at a time.
The loop is closed after a Prescaler divider that feeds the output stage the feedback divider.
SMART_ MUX
AUX_IN
/8 - /1280
Feedback Divider
Input Divider
/1 - /256
/1,/2,/5,/8,/ 10,/16,/20
Feedback Bypass Divider
PFD/
CP
1.75 GHz –
2.356 GHz
70 kHz –
400 kHz
Prescaler SYNTH
/2,/3, /4,/5
Figure 5. CDCE62002 Synthesizer Block
Output Block
Both identical output blocks incorporate a Clock Divider Module (CDM), and a universal output array buffer
driver. If an individual clock output channel is not used, then the user should disable the CDM and Output Buffer
for the unused channel to save device power. Each channel includes 4-bit in register “0” to control the divide
ratio. The output divider supports divide ratios from divide by 1 (bypass the divider) 2,3,4,5,8,10,12,16,20,24 and
32.
Sync
Pulse
Enable
Output Buffer Control
SYNTH
Digital Phase Adjust (7-bits)
/1,2,3,4C,5lock Di/v1id-e/r8Module 0/2& 1
Figure 6. CDCE62002 Output Block
UxP
LVDS
UxN
LVPECL
6
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