CDCE62002 Datasheet, PDF(22/49 Page) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

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CDCE62002

SCAS882A â JUNE 2009 â REVISED JULY 2009.............................................................................................................................................................. www.ti.com

Device Registers: Register 0

SPI RAM

BIT BIT

BIT

NAME

4 0 INBUFSELX

5 1 INBUFSELY

6 2 REFSEL

7 3 AUXSEL

8 4 ACDCSEL

9 5 TERMSEL

10 6 REFDIVIDE 0

11 7 REFDIVIDE 1

12 8 REFDIVIDE 2

13 9 REFDIVIDE 3

14 10 EXTFEEDBACK

15 11 I70TEST

16 12 ATETEST

17 13 LOCKW(0)

18 14 LOCKW(1)

19 15 OUT0DIVRSEL0

20 16 OUT0DIVRSEL1

21 17 OUT0DIVRSEL2

22 18 OUT0DIVRSEL3

23 19 OUT1DIVRSEL0

24 20 OUT1DIVRSEL1

25 21 OUT1DIVRSEL2

26 22 OUT1DIVRSEL3

27 23 HIPERORMANCE

28 24 OUTBUFSEL0X

29 25 OUTBUFSEL0Y

30 26 OUTBUFSEL1X

31 27 OUTBUFSEL1Y

Table 7. CDCE62002 Register 0 Bit Definitions

BLOCK

INBUFSELX

INBUFSELY

Smart MUX

Bits(2,3)

Input Buffers

DESCRIPTION / FUNCTION

Address 0

Address 1

Address 2

Address 3

Input Buffer Select (LVPECL,LVDS or LVCMOS)

XY(00 ) Disabled, (01) LVPECL, (10) LVDS, (11) LVCMOS

The VBB internal Biasing will be determined from this setting

See specific section for more detailed description and configuration

setup.

00 â RESERVED

10 â REF_IN Select

01â AUX_IN Select

11 â Auto Select ( Reference then AUX)

If Set to â1â DC Termination, If set to â0â AC Termination

If Set to â0â Input Buffer Internal Termination Enabled

Reference Divider Settings.

See specific section for more detailed description and configuration

setup.

TEST

PLL Lock

Output 0

Output 1

Output 0 & 1

Output 0

Output 1

External Feedback to PFD from AUX Input enabled when set to â1â

Set to â0â for Normal Operation.

Lock-detect window Bit 0

Lock-detect window Bit 1

Output 0 Divider Settings.

See specific section for more detailed description and configuration

setup.

Output 1 Divider Settings.

See specific section for more detailed description and configuration

setup.

High Performance, If this Bit is set to â1â:

â Increase the Bias in the device to achieve Best Phase Noise on the

Output Divider

â It changes the LVPECL Buffer to Hi Swing in LVPECL.

â It increases the current consumption by 20mA (Typical)

Output Buffer mode select for OUTPUT â0 â.

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

Output Buffer mode select for OUTPUT â1 â.

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

EEPROM

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Product Folder Link(s): CDCE62002

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