CDCE62002 Datasheet, PDF (27/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM
on the Rising edge of PD Pin.
FACTORY DEFAULT PROGRAMMING
The CDCE62002 is factory pre-programmed to work with 25 MHz input from the reference input or from the
auxiliary input with auto switching enabled. An internal PFD of 6.25 MHz and about 400 KHz loop bandwidth.
Output 0 is pre-programmed as an LCPECL driver to output 156.25 MHz and output 1 is pre-programmed as
LVDS driver to output 125 MHz.
25M^Mh^Hz^z
U0P
U0N
LVPECL
1₁5₅6₆.2_.25₅M_MH_hz_z
XTAL
25_5MM_hH_zz
CDCE62002
Default Programing
U1P
U1N
LVDS
1₁2₂5₅M_MH_hz
EEPROM
Register 0
Register 1
Register Content
72A000E0
8389A061
Figure 20. CDCE62002 Default Factory Programming
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE62002
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