CDCE62002 Datasheet, PDF (31/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
OUTPUT BLOCK
The output block includes two identical output channels. Each output channel comprises of a clock divider
module, and a universal output buffer as shown in Figure 26.
OUTPUT 0
Registers 0
15 16 17 18
OUTPUT 1
Registers 0
19 20 21 22
Sync
Pulse
Enable
Output Buffer Control
SYNTH
Clock Divider Module 0
UxP
LVDS
UxN
LVPECL
Clock Divider Module 1
Figure 26. CDCE62002 Output Channel
DIVIDER 0 →
DIVIDER 1 →
Table 13. CDCE62002 Output Divider Settings
OUTPUT DIVIDERS SETTING
0.18
0.17
0.16
0.15
0.22
0.21
0.20
0.19
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
DIVIDE RATIO
Disabled
/1
/2
/3
/4
/5
/6
Disabled
/8
Disabled
/10
/20
/12
/24
/16
/32
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