CDCE62002 Datasheet, PDF (18/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
INTERFACE and CONTROL BLOCK
The Interface and Control Block includes a SPI interface, four control pins, a non-volatile memory array in which
the device stores default configuration data, and an array of device registers implemented in Static RAM. This
RAM, also called the device registers, configures all hardware within the CDCE62002.
PD
SPI_ LE
SPI_ CLK
SPI_ MOSI
SPI_ MISO
Interface
&
Control
Static RAM Device Registers
Register2
Register1
Register0
Device
Hardware
EEPROM Device Registers
Register2
Register1
Register0
Figure 15. CDCE62002 Interface and Control Block
18
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