CDCE62002 Datasheet, PDF (41/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
CLOCKING ADCS WITH THE CDCE62002
High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample
clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly
implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation
trend often causes engineers working in communications system design to encounter the term “clock limited
performance”. Therefore, it is important to understand the impact of clock jitter on ADC performance. The
following equation shows the relationship of data converter signal to noise ratio (SNR) to total jitter:
SNR _jitter
= 20log₁₀
é
ê
ë
2p
1
f_in jitter_total
ù
ú
û
(4)
Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample
clock:
jitter_total = (jitter_ADC )² + (jitter_CLK )²
(5)
With respect to an ADC with N-bits of resolution, ignoring total jitter, ADC quantization error, and input noise, the
following equation shows the relationship between resolution and SNR:
SNR _ADC = 6.02N + 1.76
(6)
Figure 35 plots Equation 4 and Equation 6 for constant values of total jitter. When used in conjunction with most
ADCs, the CDCE62002 supports a total jitter performance value of <1ps.
Data Converter Jitter Requirements
140
130
120
110
100
90
80
1ps
70
60
50
40
30
20
10
0
1
350 fs
100 fs
50 fs
10
100
1000
Input Bandwidth (MHz)
Figure 35. Data Converter Jitter Requirements
26
24
22
20
18
16
14
12
10
8
6
4
2
0
10000
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