CDCE62002 Datasheet, PDF (16/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
SPI CONTROL INTERFACE TIMING
t1
t4
t5
SPI _CLK
SPI _MOSI
Bit0
SPI_LE
t2
t3
Bit1
Bit29
Bit30
Bit31
t7
t6
Figure 12. Timing Diagram for SPI Write Command
t4
t5
SPI _CLK
SPI _MOSI
Bit 30
t2
t3
Bit 31
SPI _MISO
SPI_LE
Bit 0
Bit 1
Bit 2
t7
t6
t8
Figure 13. Timing Diagram for SPI Read Command
f_Clock
t₁
t₂
t₃
t₄
t₅
t₆
t₇
t₈
Table 5. SPI Bus Timing Characteristics
SPI BUS TIMINGS
PARAMETER
Clock Frequency for the SPI_CLK
SPI_LE to SPI_CLK setup time
SPI_MOSI to SPI_CLK setup time
SPI_MOSI to SPI_CLK hold time
SPI_CLK high duration
SPI_CLK low duration
SPI_CLK to SPI_LE Setup time
SPI_LE Pulse Width
SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE)
MIN TYP
10
10
10
25
25
10
20
10
MAX
20
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
16
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