CDCE62002 Datasheet, PDF (2/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurability
via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for
clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5
ps RMS⁽¹⁾. It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block
including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock
distribution block includes two individually programmable outputs that can be configured to provide different
combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique
output frequency (ranging from 10.94 MHz to 1.175 GHz⁽²⁾). If Both outputs are configured in single-ended mode
(e.g., LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential
inputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be connected to a
CMOS level clock or configured to connect to an external AT-Cut crystal via an on board oscillator block. The
smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the
synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select
between the highest priority input clock available.
Data
SERDES ^{Cleaned Clock}
Recovered Clock
CDCE 62002
ASIC Clock
ASIC
Figure 1. CDCE62002 Application Example
(1) 10 kHz to 20 MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.
2
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