CDCE62002 Datasheet, PDF (32/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
SYNTHESIZER BLOCK
Figure 27 provides an overview of the CDCE62002 synthesizer block. The Synthesizer Block provides a Phase
Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The
synthesizer block generates an output clock called “SYNTH” and drives it onto the Internal Clock Distribution
Bus.
Input Divider Settings
Register 1
876 54321
SMART _MUX
Input Divider
/1 - /256
Loop Filter and Charge Pump
Current Settings
Register 1
25 24 23 22
1.75 GHz –
2.356 GHz
Prescaler
Register 1
98
Feedback Divider
/8 - /1280
/1,/2,/5,/8,/10,/16,/20
PFD /
CP
Register 1
18 17 16 15 14 13 12 11
Feedback Divider
Register 1
21 20 19
Feedback Bypass Divider
70 kHz –
400 kHz
Register 1
0
VCO Select
Prescaler SYNTH
/2,/3,/4,/5
Figure 27. CDCE62002 Synthesizer Block
Input Divider
The Input Divider divides the clock signal selected by the Smart Multiplexer and presents the divided signal to
the Phase Frequency Detector / Charge Pump of the frequency synthesizer.
SELINDIV7
1.8
0
0
0
0
0
0
–
–
1
SELINDIV6
1.7
0
0
0
0
1
1
–
–
1
Table 14. CDCE62002 Input Divider Settings
SELINDIV5
1.6
0
0
0
0
0
0
–
–
1
INPUT DIVIDER SETTINGS
SELINDIV4 SELINDIV3
1.5
1.4
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
1
1
SELINDIV2
1.3
0
0
0
0
1
1
–
–
1
SELINDIV1
1.2
0
0
1
1
0
0
–
–
1
SELINDIV0
1.1
0
1
0
1
0
1
–
–
1
DIVIDE
RATIO
1
2
3
4
5
6
–
–
256
32
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