CDCE62002 Datasheet, PDF (26/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
Device Control
Figure 19 provides a conceptual explanation of the CDCE62002 Device operation. Table 11 defines how the
device behaves in each of the operational states.
Power ON
Reset
Power
Applied
Delay
Finished
Device
OFF
PLLRESET= ON
VCO
CAL
Power Down
Power Down = ON
Active Mode
Sync = ON
Sync = OFF
Sync
Figure 19. CDCE62002 Device State Control Diagram
State
Power-On
Reset
VCO CAL
Active Mode
Power Down
Sync
Table 11. CDCE62002 Device State Definitions
Device Behavior
Entered Via
Exited Via
After device power supply reaches
approximately 2.35V, the contents of
EEPROM are copied into the Device
Registers, thereby initializing the device
hardware .
Power applied to the device or
upon exit from Power Down State
via the PD pin set HIGH.
The voltage controlled oscillator is
calibrated based on the PLL settings
and the incoming reference clock. After
the VCO has been calibrated, the device
enters Active Mode automatically.
Delay process in the Power-On
Reset State is finished or
PLLRESET=ON
Normal Operation
CAL Done (VCO calibration
process finished) or Sync = OFF
(from Sync State).
Used to shut down all hardware and
Resets the device after exiting the
Power Down State. Therefore, the
EEPROM contents will eventually be
copied into RAM after the Power Down
State is exited.
PD pin is pulled LOW.
Sync synchronizes both outputs dividers Sync Bit in device register 2 bit 8
so that they begin counting at the same is set LOW
time
Power On Reset and EEPROM
loading delays are finished OR the
PD pin is set LOW.
Calibration Process in completed
Power Down or PLLRESET=ON
PD pin is pulled HIGH.
Sync bit in device register 2 bit 8 is
set HIGH
SPI Port PLL
Status Status
OFF Disabled
Output
Divider
Status
Disabled
ON Enabled Disabled
ON Enabled Disabled
or
Enabled
ON Disabled Disabled
ON Enabled Disabled
Output
Buffer
Status
OFF
OFF
Disabled or
Enabled
Disabled
Disabled
External Control Pins
Power Down (PD)
When pulled LOW, PD activates the Power Down state which shuts down all hardware and resets the device.
Restoring PD high will cause the CDCE62002 to exit the Power Down State. This causes the device to behave
as if it has been powered up including copying the EEPROM contents into RAM. PD pin also has a shadowed
PD bit residing in Register 2 Bit 7. When asserted Low it puts the device in Power Down Mode, but it does not
load the EEPROM when the bits is disserted.
NOTE:
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