CDCE62002 Datasheet, PDF (4/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
SCAS882A – JUNE 2009 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
FUNCTIONAL DESCRIPTION
EXT _LFP
EXT _LFN
REF_IN
XTAL /
AUX _IN
Reference
Divider
Input
Divider
Feedback
Divider
PFD /
CP
Output
Divider 0
Prescaler
Output
Divider 1
U0 P
U0 N
U1 P
U1 N
PD
SPI_ LE
SPI _CLK
SPI _MOSI
SPI _MISO
Interface
&
Control
EEPROM
Figure 2. CDCE62002 Block Diagram
The CDCE62002 comprises of four primary blocks: the interface and control block, the input block, the output
block, and the synthesizer block. In order to determine which settings are appropriate for any specific
combination of input/output frequencies, a basic understanding of these blocks is required. The interface and
control block determines the state of the CDCE62002 at power-up based on the contents of the on-board
EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62002 by writing directly
to the device registers after power-up. The input block selects which of the two input ports is available for use by
the synthesizer block. The output block provides two separate clock channels that are fully programmable. The
synthesizer block multiplies and filters the input clock selected by the input block.
NOTE:
This Section of the data sheet provides a high-level description of the features of the
CDCE62002 for purpose of understanding its capabilities. For a complete description
of device registers and I/O, refer to the Device Configuration Section.
4
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