CDCE62002 Datasheet, PDF (19/49 Pages) Texas Instruments – Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

CDCE62002
www.ti.com.............................................................................................................................................................. SCAS882A – JUNE 2009 – REVISED JULY 2009
SPI (Serial Peripheral Interface)
The serial interface of CDCE62002 is a simple bidirectional SPI interface for writing and reading to and from the
device registers. It implements a low speed serial communications link in a master/slave topology in which the
CDCE62002 is a slave. The SPI consists of four signals:
• SPI_CLK: Serial Clock (Output from Master) – the CDCE62002 clocks data in and out on the rising edge of SPI_CLK. Data transitions
therefore occur on the falling edge of the clock.
• SPI_MOSI: Master Output Slave Input (Output from Master).
• SPI_MISO: Master Input Slave Output (Output from Slave)
• SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can take
place.
The CDCE62002 implements data fields that are 28-bits wide. In addition, it contains 3 registers, each
comprising a 28 bit data field. Therefore, accessing the CDCE62002 requires that the host program append a
4-bit address field to the front of the data field as follows:
Device Register N
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI Master (Host)
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_LE
Last in /
Last out
SPI Register
Data Bits (28)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address
Bits
(4)
3 210
First In/
First Out
SPI Slave (CDCE62002)
SPI _CLK
SPI _MOSI
SPI _MISO
SPI _LE
SPI_CLK
SPI _MOSI
SPI _LE
SPI _MISO
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
Figure 16. CDCE62002 SPI Communications Format
Copyright © 2009, Texas Instruments Incorporated
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