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CD00191174 Datasheet, PDF (97/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14381b
5.3.19
1. VREF+ and VREF- inputs are available only on 100-pin packages.
DAC electrical specifications
Table 59. DAC characteristics
Symbol
Parameter
Min Typ
Max(1)
Unit
Comments
VDDA
Analog supply voltage
2.4
3.6
V
VREF+
VSSA
RLOAD(2)
RO(2)
Reference supply voltage
2.4
Ground
0
Resistive load with buffer ON 5
Impedance output with buffer
OFF
3.6
V
VREF+ must always be below
VDDA
0
V
kΩ
When the buffer is OFF, the
15
kΩ
minimum resistive load
between DAC_OUT and VSS to
have a 1% accuracy is 1.5 MΩ
CLOAD(2)
Capacitive load
Maximum capacitive load at
50
pF DAC_OUT pin (when the buffer
is ON).
DAC_OUT
min(2)
Lower DAC_OUT voltage with
buffer ON
0.2
DAC_OUT Higher DAC_OUT voltage with
max(2)
buffer ON
V
VDDA – 0.2 V
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
VREF+ = 3.6 V and (0x155) and
(0xEAB) at VREF+ = 2.4 V.
DAC_OUT
min(2)
DAC_OUT
max(2)
Lower DAC_OUT voltage with
buffer OFF
Higher DAC_OUT voltage with
buffer OFF
0.5
mV
It gives the maximum output
VREF+ – 1LSB V
excursion of the DAC.
Doc ID 14610 Rev 8
97/112