CD00191174 Datasheet, PDF (59/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings^{(1) (2)}
Symbol
Parameter
Min
Max
Unit
t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low
t_w(NADV)
FSMC_NADV low time
1. C_L = 15 pF.
2. Based on characterization, not tested in production.
5
ns
t_HCLK + 1.5 ns
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
FSMC_NEx
t_w(NE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0]
FSMC_D[15:0]
FSMC_NADV⁽¹⁾
t_{v(NWE_NE)}
t_w(NWE)
t_{v(A_NE)}
t_{v(BL_NE)}
t_{v(Data_NE)}
t _{v(NADV_NE)}
t_w(NADV)
t_{h(A_NWE)}
Address
t_{h(BL_NWE)}
NBL
t_{h(Data_NWE)}
Data
t _{h(NE_NWE)}
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
FSMC_NE low time
3t_HCLK – 1 3t_HCLK + 2 ns
t_{v(NWE_NE)} FSMC_NEx low to FSMC_NWE low
t_HCLK – 0.5 t_HCLK + 1.5 ns
t_w(NWE)
FSMC_NWE low time
t_HCLK – 0.5 t_HCLK + 1.5 ns
t_{h(NE_NWE)} FSMC_NWE high to FSMC_NE high hold time t_HCLK
ns
t_{v(A_NE)}
FSMC_NEx low to FSMC_A valid
7.5
ns
t_{h(A_NWE)} Address hold time after FSMC_NWE high
t_HCLK
ns
t_{v(BL_NE)}
FSMC_NEx low to FSMC_BL valid
1.5
ns
t_{h(BL_NWE)} FSMC_BL hold time after FSMC_NWE high t_HCLK – 0.5
ns
t_{v(Data_NE)} FSMC_NEx low to Data valid
t_HCLK + 7
ns
t_{h(Data_NWE)} Data hold time after FSMC_NWE high
t_HCLK
ns
Doc ID 14610 Rev 8
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