English
Language : 

CD00191174 Datasheet, PDF (93/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU
◁
STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 55. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
VDDA
VREF+
IVREF
Power supply
Positive reference voltage
Current on the VREF input
pin
fADC
fS(2)
ADC clock frequency
Sampling rate
fTRIG(2) External trigger frequency
fADC = 14 MHz
2.4
2.4
0.6
0.05
160(1)
VAIN Conversion voltage range(3)
0 (VSSA or VREF-
tied to ground)
3.6
VDDA
220(1)
14
1
823
17
VREF+
V
V
µA
MHz
MHz
kHz
1/fADC
V
RAIN(2) External input impedance
See Equation
1 and Table 56
for details
50
kΩ
RADC(2) Sampling switch resistance
CADC(2)
Internal sample and hold
capacitor
1
kΩ
8
pF
tCAL(2) Calibration time
tlat(2)
Injection trigger conversion
latency
tlatr(2)
Regular trigger conversion
latency
tS(2) Sampling time
tSTAB(2) Power-up time
tCONV(2)
Total conversion time
(including sampling time)
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
fADC = 14 MHz
5.9
83
0.107
1.5
0
0
0.214
3(4)
0.143
2(4)
17.1
239.5
1
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
1/fADC
µs
fADC = 14 MHz
1
18
µs
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 3: Pinouts and pin descriptions for further details.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 55.
Equation 1: RAIN max formula:
RAIN
<
----------------------------T----S-----------------------------
fADC × CADC × ln (2N + 2)
–
RADC
Doc ID 14610 Rev 8
93/112
 ▷