CD00191174 Datasheet, PDF (85/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
5.3.15
Figure 43. I/O AC characteristics definition
90%
50%
10%
10%
50%
90%
EXT ERNAL
O UTP UT
ON 50pF
tr(I _O)out
tr(I _O)out
T
Maximum fr equency is achieved if (tr + tf) ≤ 2/3) T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R_PU (see Table 46).
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under ambient temperature and V_DD supply voltage conditions summarized in
Table 10.
Table 49. NRST pin characteristics
Symbol
Parameter
Conditions Min Typ
Max Unit
V_IL(NRST)(1) NRST Input low level voltage
V_IH(NRST)(1) NRST Input high level voltage
–0.5
2
0.8
V
V_DD+0.5
V_hys(NRST)
NRST Schmitt trigger voltage
hysteresis
200
mV
R_PU
Weak pull-up equivalent resistor⁽²⁾ V_IN = V_SS
30
40
V_F(NRST)(1) NRST Input filtered pulse
V_NF(NRST)(1) NRST Input not filtered pulse
300
50
kΩ
100
ns
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
. the series resistance must be minimum (~10% order)
Figure 44. Recommended NRST pin protection
%XTERNAL
RESETCIRCUIT^
6$$
.234^
205
—&
)NTERNAL2ESET
&ILTER
34-&XXX
AIC
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST) max level specified in
Table 49. Otherwise the reset will not be taken into account by the device.
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