CD00191174 Datasheet, PDF (89/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests
performed under ambient temperature, f_PCLKx frequency and V_DD supply voltage conditions
summarized in Table 10.
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 53. STM32F10xxx SPI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
f_SCK
1/t_c(SCK)
Master mode
SPI clock frequency
Slave mode
10
MHz
10
t_r(SCK)
t_f(SCK)
SPI clock rise and
fall time
Capacitive load: C = 30 pF
8
t_su(NSS)(1) NSS setup time
Slave mode
4t_PCLK
t_h(NSS)(1) NSS hold time
Slave mode
73
t_w(SCKH)(1) SCK high and low
t_w(SCKL)(1) time
Master mode, f_PCLK = 36 MHz,
presc = 4
50
60
Master mode - SPI1
3
t_su(MI) ⁽¹⁾ Data input setup
t_su(SI)(1) time
Master mode - SPI2
5
Slave mode
4
Master mode - SPI1
t_h(MI) ⁽¹⁾
Data input hold time Master mode - SPI2
t_h(SI)(1)
Slave mode
t_a(SO)(1)(2)
Data output access
time
Slave mode, f_PCLK = 36 MHz,
presc = 4
Slave mode, f_PCLK = 20 MHz
t_{dis(SO)(1)(3)}
Data output disable
time
Slave mode
4
6
5
ns
0
55
4t_PCLK
10
t_v(SO) ⁽¹⁾
Data output valid
time
Slave mode (after enable edge)
25
t_v(MO)(1)
Data output valid
time
Master mode (after enable edge)
6
t_{h(SO)(1) Data output hold}
Slave mode (after enable edge)
25
t_h(MO)(1) ^time
Master mode (after enable edge)
6
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Doc ID 14610 Rev 8
89/112