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CD00191174 Datasheet, PDF (40/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU
Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
5.3.4
5.3.5
Embedded reference voltage
The parameters given in Table 13 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
Table 13. Embedded internal reference voltage
Symbol
Parameter
Conditions
Min Typ Max Unit
VREFINT Internal reference voltage
–40 °C < TA < +85 °C 1.16 1.20 1.24 V
TS_vrefint(1)
ADC sampling time when reading
the internal reference voltage
5.1 17.1(2) µs
VRERINT(2)
Internal reference voltage spread
over the temperature range
VDD = 3 V ±10 mV
10 mV
TCoeff(2) Temperature coefficient
100
ppm/
°C
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled except if it is explicitly mentioned
● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 36 MHz)
● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
● When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 14 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 10.
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