CD00191174 Datasheet, PDF (58/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
&3-#?.%
&3-#?./%
T _V./%?.%
T_W.%
T _W./%
T _H.%?./%
&3-#?.7%
&3-#?!;=
&3-#?.",;=
T_V!?.%
T_V",?.%
!DDRESS
T _H!?./%
T _H",?./%
&3-#?$;=
&3-#?.!$6 ^
T _V.!$6?.%
T_W.!$6
T_SU$ATA?./%
T_SU$ATA?.%
$ATA
T _H$ATA?.%
T_H$ATA?./%
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
-36
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings^{(1) (2)}
Symbol
Parameter
Min
Max
Unit
t_w(NE)
FSMC_NE low time
5t_HCLK – 1.5 5t_HCLK + 2
ns
t_{v(NOE_NE)} FSMC_NEx low to FSMC_NOE low
0.5
1.5
ns
t_w(NOE)
FSMC_NOE low time
5t_HCLK – 1.5 5t_HCLK + 1.5 ns
t_{h(NE_NOE)} FSMC_NOE high to FSMC_NE high hold time –1.5
ns
t_{v(A_NE)}
FSMC_NEx low to FSMC_A valid
7
ns
t_{h(A_NOE)} Address hold time after FSMC_NOE high
0.1
ns
t_{v(BL_NE)}
FSMC_NEx low to FSMC_BL valid
0
ns
t_{h(BL_NOE)} FSMC_BL hold time after FSMC_NOE high 0
ns
t_{su(Data_NE)} Data to FSMC_NEx high setup time
2t_HCLK + 25
ns
t_{su(Data_NOE)} Data to FSMC_NOEx high setup time
2t_HCLK + 25
ns
t_{h(Data_NOE)} Data hold time after FSMC_NOE high
0
ns
t_{h(Data_NE)} Data hold time after FSMC_NEx high
0
ns
58/112
Doc ID 14610 Rev 8