CD00191174 Datasheet, PDF (13/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

STM32F101xC, STM32F101xD, STM32F101xE
Figure 2. Clock tree
Description
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
8 MHz
HSI RC
HSI
/2
PLLSRC _PLLMUL
..., x16
x2, x3, x4
PLL
FLITFCLK
to Flash programming interface
Peripheral clock
FSMCCLK _{to FSMC}
enable
36 MHz max
HCLK
to AHB bus, core,
Clock
memory and DMA
SW
Enable (7 bits)
/8
to Cortex System timer
FCLK Cortex
HSI
PLLCLK
HSE
SYSCLK AHB
36 MHz ^Prescaler
max ^{/1, 2..512}
APB1
Prescaler
/1, 2, 4, 8, 16
free running clock
36 MHz max
PCLK1
to APB1
Peripheral Clock ^peripherals
Enable (18 bits)
CSS
TIM2,3,4,5,6,7
If (APB1 prescaler =1) x1
else x2
to TIM2,3,4,5,6 and 7
TIMXCLK
Peripheral Clock
Enable (6 bits)
4-16 MHz
HSE OSC
PLLXTPRE
/2
APB2
Prescaler
/1, 2, 4, 8, 16
36 MHz max
PCLK2
peripherals to APB2
Peripheral Clock
Enable (11 bits)
LSE OSC
32.768 kHz
/128
LSE
to RTC
RTCCLK
ADC
Prescaler
/2, 4, 6, 8
to ADC
ADCCLK
RTCSEL[1:0]
LSI RC
40 kHz
LSI
to Independent Watchdog (IWDG)
IWDGCLK
MCO
Main
/2
Clock Output
MCO
PLLCLK
HSI
HSE
SYSCLK
Legend:
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
ai15100
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.
2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.
Doc ID 14610 Rev 8
13/112