CD00191174 Datasheet, PDF (60/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low
t_w(NADV)
FSMC_NADV low time
1. C_L = 15 pF.
2. Based on characterization, not tested in production.
5.5
ns
t_HCLK + 1.5 ns
Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms
t_w(NE)
FSMC_NE
t_{v(NOE_NE)}
t _{h(NE_NOE)}
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
t _w(NOE)
t_{v(A_NE)}
t_{v(BL_NE)}
Address
NBL
t_{h(A_NOE)}
t_{h(BL_NOE)}
t _{v(A_NE)}
Address
t _{v(NADV_NE)}
t_w(NADV)
t_{su(Data_NE)}
t_{su(Data_NOE)}
Data
t_{h(AD_NADV)}
t_{h(Data_NE)}
t_{h(Data_NOE)}
FSMC_NADV
ai14892b
Table 33. Asynchronous multiplexed NOR/PSRAM read timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE)
FSMC_NE low time
7t_HCLK – 2 7t_HCLK + 2
ns
t_{v(NOE_NE)} FSMC_NEx low to FSMC_NOE low
3t_HCLK – 0.5 3t_HCLK + 1.5 ns
t_w(NOE)
FSMC_NOE low time
4t_HCLK – 1 4t_HCLK + 2
ns
t_{h(NE_NOE)} FSMC_NOE high to FSMC_NE high hold time –1
ns
t_{v(A_NE)}
FSMC_NEx low to FSMC_A valid
0
ns
t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low
3
5
ns
t_w(NADV)
FSMC_NADV low time
t_HCLK –1.5 t_HCLK + 1.5 ns
t_{h(AD_NADV)}
FSMC_AD (address) valid hold time after
FSMC_NADV high
t_HCLK
ns
t_{h(A_NOE)}
Address hold time after FSMC_NOE high
t_HCLK
ns
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Doc ID 14610 Rev 8