CD00191174 Datasheet, PDF (87/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Table 51. I²C characteristics
Symbol
Parameter
Standard mode I²C⁽¹⁾ Fast mode I²C⁽¹⁾⁽²⁾
Unit
Min
Max
Min
Max
t_w(SCLL)
t_w(SCLH)
t_su(SDA)
t_h(SDA)
t_r(SDA)
t_r(SCL)
t_f(SDA)
t_f(SCL)
t_h(STA)
t_su(STA)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition setup
time
4.7
1.3
µs
4.0
0.6
250
100
0⁽³⁾
0⁽⁴⁾
900⁽³⁾
1000 20+0.1C_b 300
ns
300
300
4.0
0.6
µs
4.7
0.6
t_su(STO) Stop condition setup time
4.0
t_w(STO:STA)
Stop to Start condition time (bus
free)
4.7
0.6
µs
1.3
µs
C_b
Capacitive load for each bus line
400
400 pF
1. Guaranteed by design, not tested in production.
2.
ft_{PoCaLcKh1iemvuestthbeefahsigthmeor dtheaIn2C2}
MHz to achieve standard mode I²C frequencies.
frequencies and it must be a multiple of 10 MHz
It must be
in order to
higher
reach
than 4 MHz
the I2C fast
mode maximum clock speed of 400 kHz.
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
Doc ID 14610 Rev 8
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