CD00191174 Datasheet, PDF (74/112 Pages) STMicroelectronics – High-density access line, ARM-based 32-bit MCU

Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
Table 39. Switching characteristics for PC Card/CF read and write cycles⁽¹⁾⁽²⁾ (continued)
Symbol
Parameter
Min
Max
Unit
t_d(D-NWE)
FSMC_D[15:0] valid before FSMC_NWE high
t_w(NIOWR)
FSMC_NIOWR low width
t_v(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
t_h(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
t_{d(NCE4_1-NIOWR)} FSMC_NCE4_1 low to FSMC_NIOWR valid
t_{h(NCEx-NIOWR)} FSMC_NCEx high to FSMC_NIOWR invalid
t_{h(NCE4_1-NIOWR)} FSMC_NCE4_1 high to FSMC_NIOWR invalid
t_{d(NIORD-NCEx)} FSMC_NCEx low to FSMC_NIORD valid
t_{d(NIORD-NCE4_1)} FSMC_NCE4_1 low to FSMC_NIORD valid
t_{h(NCEx-NIORD)} FSMC_NCEx high to FSMC_NIORD invalid
t_{h(NCE4_1-NIORD)} FSMC_NCE4_1 high to FSMC_NIORD invalid
t_su(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
t_d(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high
t_w(NIORD)
FSMC_NIORD low width
1. C_L = 15 pF.
2. Based on characterization, not tested in production.
13t_HCLK
ns
8t_HCLK + 3
ns
5t_HCLK +1
ns
11t_HCLK
ns
5t_HCLK+3ns ns
5t_HCLK – 5
ns
5t_HCLK + 2.5 ns
5t_HCLK – 5
ns
4.5
ns
9
ns
8t_HCLK + 2
ns
NAND controller waveforms and timings
Figure 35 through Figure 38 represent synchronous waveforms and Table 40 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
● COM.FSMC_SetupTime = 0x01;
● COM.FSMC_WaitSetupTime = 0x03;
● COM.FSMC_HoldSetupTime = 0x02;
● COM.FSMC_HiZSetupTime = 0x01;
● ATT.FSMC_SetupTime = 0x01;
● ATT.FSMC_WaitSetupTime = 0x03;
● ATT.FSMC_HoldSetupTime = 0x02;
● ATT.FSMC_HiZSetupTime = 0x01;
● Bank = FSMC_Bank_NAND;
● MemoryDataWidth = FSMC_MemoryDataWidth_16b;
● ECC = FSMC_ECC_Enable;
● ECCPageSize = FSMC_ECCPageSize_512Bytes;
● TCLRSetupTime = 0;
● TARSetupTime = 0;
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Doc ID 14610 Rev 8