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CD00237391 Datasheet, PDF (96/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM
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Electrical characteristics
STM32F20xxx
5.3.16 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 12. All I/Os are CMOS and TTL
compliant.
Table 44. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
VIH(1)
Input low level voltage
TT(2) I/O input high level voltage
FT(3) I/O input high level voltage
VSS–0.3
-
0.8
TTL ports
2.0
2.7 V ≤ VDD ≤ 3.6 V
-
VDD+0.3
2.0
-
5.5
VIL Input low level voltage
TT I/O input high level voltage
VIH(1)
FT I/O input high level voltage
CMOS ports
VSS–0.3
-
0.3VDD
V
-
3.6(4)
1.8 V ≤ VDD ≤ 3.6 V
-
5.2(4)
0.7VDD
CMOS ports
2.0 V ≤ VDD ≤ 3.6 V
-
5.5(4)
I/O Schmitt trigger voltage hysteresis(5)
-
200
-
Vhys IO FT Schmitt trigger voltage
hysteresis(5)
5% VDD(4)
-
mV
-
I/O input leakage current (6)
Ilkg I/O FT input leakage current (6)
VSS ≤ VIN ≤ VDD
VIN = 5 V
-
-
±1
µA
-
-
3
All pins
except for
RPU
Weak pull-up equivalent PA10 and
resistor(7)
PB12
VIN = VSS
30
40
50
RPD
Weak pull-down
equivalent resistor
PA10 and
PB12
All pins
except for
PA10 and
PB12
VIN = VDD
8
11
15
kΩ
30
40
50
PA10 and
PB12
8
11
15
CIO(8) I/O pin capacitance
5
pF
1. If VIH maximum value cannot be respected, the injection current must be limited externally to IINJ(PIN) maximum value.
2. TT = 3.6 V tolerant.
3. FT = 5 V tolerant.
4. With a minimum of 100 mV.
5. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
8. Guaranteed by design, not tested in production.
96/177
Doc ID 15818 Rev 9
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