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CD00237391 Datasheet, PDF (100/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM
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Electrical characteristics
STM32F20xxx
5.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 44).
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 12.
Table 47. NRST pin characteristics
Symbol
Parameter
Conditions
Min Typ Max Unit
VIL(NRST)(1)
VIH(NRST)(1)
VIL(NRST)(1)
VIH(NRST)(1)
NRST input low level voltage
NRST input high level voltage
NRST input low level voltage
NRST input high level voltage
TTL ports
VSS−0.3 -
0.8
V
2.7 V ≤ VDD ≤ 3.6 V
2
- VDD+0.3
CMOS ports
VSS−0.3 -
0.3VDD
V
1.8 V ≤ VDD ≤ 3.6 V 0.7VDD
- VDD+0.3
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
RPU
VF(NRST)(1)
VNF(NRST)(1)
Weak pull-up equivalent resistor(2)
NRST Input filtered pulse
NRST Input not filtered pulse
VIN = VSS
VDD > 2.7 V
30
40
50
kΩ
-
-
100
ns
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal Reset source 20
-
-
µs
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
Figure 37. Recommended NRST pin protection
External
reset circuit(1)
VDD
NRST(2)
RPU
0.1 μF
Internal Reset
Filter
STM32Fxxx
ai14132c
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 47. Otherwise the reset is not taken into account by the device.
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Doc ID 15818 Rev 9
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