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CD00237391 Datasheet, PDF (171/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM
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STM32F20xxx
Revision history
Table 94. Document revision history (continued)
Date
Revision
Changes
22-Apr-2011
Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and
tf(SCK) to tf(SCL) in Table 50: I2C characteristics and in Figure 38: I2C
bus AC waveforms and measurement circuit.
Added Table 55: USB OTG FS DC electrical characteristics and
updated Table 56: USB OTG FS electrical characteristics.
Updated VDD minimum value in Table 60: Ethernet DC electrical
characteristics.
Updated Table 64: ADC characteristics and RAIN equation.
Updated RAIN equation. Updated Table 66: DAC characteristics.
Updated tSTART in Table 67: TS characteristics.
Updated R typical value in Table 68: VBAT monitoring characteristics.
Updated Table 69: Embedded internal reference voltage.
Modified FSMC_NOE waveform in Figure 54: Asynchronous non-
multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-
AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-
6
NWEH), and updated data latency from 1 to 0 in Figure 58:
Synchronous multiplexed NOR/PSRAM read timings, Figure 59:
(continued) Synchronous multiplexed PSRAM write timings, Figure 60:
Synchronous non-multiplexed NOR/PSRAM read timings, and
Figure 61: Synchronous non-multiplexed PSRAM write timings,
Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV),
td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and
modified tw(CLK) minimum value in Table 74, Table 75, Table 76, and
Table 77.
Updated note 2 in Table 70, Table 71, Table 72, Table 73, Table 74,
Table 75, Table 76, and Table 77.
Modified th(NIOWR-D) in Figure 67: PC Card/CompactFlash controller
waveforms for I/O space write access.
Modified FSMC_NCEx signal in Figure 68: NAND controller
waveforms for read access, Figure 69: NAND controller waveforms for
write access, Figure 70: NAND controller waveforms for common
memory read access, and Figure 71: NAND controller waveforms for
common memory write access
Specified Full speed (FS) mode for Figure 89: USB OTG HS
peripheral-only connection in FS mode and Figure 90: USB OTG HS
host-only connection in FS mode.
Doc ID 15818 Rev 9
171/177
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