CD00237391 Datasheet, PDF (131/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

STM32F20xxx
Electrical characteristics
Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK)
tw(CLK)
BUSTURN = 0
FSMC_CLK
td(CLKL-NExL)
FSMC_NEx
Data latency = 0
td(CLKL-NExH)
td(CLKL-NADVL)
FSMC_NADV
td(CLKL-NADVH)
FSMC_A[25:0]
td(CLKL-AV)
td(CLKL-AIV)
FSMC_NOE
FSMC_D[15:0]
td(CLKH-NOEL) td(CLKL-NOEH)
tsu(DV-CLKH)
tsu(NWAITV-CLKH)
th(CLKH-DV)
tsu(DV-CLKH)
D1
D2
th(CLKH-DV)
th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
tsu(NWAITV-CLKH)
t _{h(CLKH-NWAITV)}
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
ai14894g
Table 76. Synchronous non-multiplexed NOR/PSRAM read timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max Unit
t_w(CLK)
FSMC_CLK period
t_d(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
t_d(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
t_{d(CLKL-NADVL)} FSMC_CLK low to FSMC_NADV low
t_{d(CLKL-NADVH)} FSMC_CLK low to FSMC_NADV high
t_d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
t_d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
t_d(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low
t_d(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high
t_su(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high
t_h(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
2T_HCLK
-
ns
-
0
ns
1
-
ns
-
2.5 ns
4
-
ns
-
0
ns
3
-
ns
-
1
ns
1.5
-
ns
8
-
ns
3.5
-
ns
Doc ID 15818 Rev 9
131/177