CD00237391 Datasheet, PDF (175/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

STM32F20xxx
Revision history
Table 94. Document revision history (continued)
Date
Revision
Changes
29-Oct-2012
Changed minimum supply voltage from 1.65 to 1.8 V.
Updated number of AHB buses in Section 2: Description and
Section 2.2.12: Clocks and startup.
Removed Figure 4. Compatible board design between STM32F10xx
and STM32F2xx for LQFP176 package.
Updated Note 2 below Figure 4: STM32F20x block diagram.
Changed System memory to System memory + OTP in Figure 14:
Memory map.
Added Note 1 below Table 14: VCAP1/VCAP2 operating conditions.
Updated V_DDA and V_REF+ decouping capacitor in Figure 17: Power
supply scheme and updated Note 3.
Changed simplex mode into half-duplex mode in Section 2.2.24: Inter-
integrated sound (I2S).
Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and
DAC_OUT2, respectively.Changed TIM2_CH1/TIM2_ETR into
TIM2_CH1_ETR for PA0 and PA5 in Table 8: Alternate function
mapping.
Updated note applying to I_DD (external clock and all peripheral
disabled) in Table 18: Typical and maximum current consumption in
Run mode, code with data processing running from Flash memory
(ART accelerator disabled). Updated Note 3 below Table 20: Typical
and maximum current consumption in Sleep mode.
10
Removed f_{HSE_ext} typical value in Table 26: High-speed external user
clock characteristics.
Updated master I2S clock jitter conditions and vlaues in Table 33:
PLLI2S (audio PLL) characteristics.
Updated equations in Section 5.3.11: PLL spread spectrum clock
generation (SSCG) characteristics.
Swapped TTL and CMOS port conditions for V_OL and V_OH in Table 45:
Output voltage characteristics.
Updated V_IL(NRST) and V_IH(NRST) in Table 47: NRST pin characteristics.
Updated Table 52: SPI characteristics and Table 53: I2S
characteristics. Removed note 1 related to measurement points below
Figure 40: SPI timing diagram - slave mode and CPHA = 1, Figure 41:
SPI timing diagram - master mode, and Figure 42: I2S slave timing
diagram (Philips protocol)(1).
Updated t_HC in Table 59: ULPI timing.
Updated Figure 46: Ethernet SMI timing diagram, Table 61: Dynamics
characteristics: Ethernet MAC signals for SMI and Table 63: Dynamics
characteristics: Ethernet MAC signals for MII.
Update f_TRIG in Table 64: ADC characteristics.
Updated I_DDA description in Table 66: DAC characteristics.
Updated note below Figure 51: Power supply and reference
decoupling (VREF+ not connected to VDDA) and Figure 52: Power
supply and reference decoupling (VREF+ connected to VDDA).
Doc ID 15818 Rev 9
175/177