CD00237391 Datasheet, PDF (126/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

Electrical characteristics
STM32F20xxx
Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms
t_w(NE)
FSMC_NE
t_{v(NOE_NE)}
t _{h(NE_NOE)}
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
FSMC_NADV
t _w(NOE)
t_{v(A_NE)}
t_{v(BL_NE)}
Address
NBL
t_{h(A_NOE)}
t_{h(BL_NOE)}
t _{v(A_NE)}
Address
t _{v(NADV_NE)}
t_w(NADV)
t_{su(Data_NE)}
t_{su(Data_NOE)}
Data
t_{h(AD_NADV)}
t_{h(Data_NE)}
t_{h(Data_NOE)}
ai14892b
Table 72. Asynchronous multiplexed PSRAM/NOR read timings⁽¹⁾⁽²⁾
Symbol
Parameter
Min
Max
Unit
t_w(NE) FSMC_NE low time
3T_HCLK-1
3T_HCLK+1
ns
t_{v(NOE_NE)} FSMC_NEx low to FSMC_NOE low
2T_HCLK
2T_HCLK+0.5
ns
t_w(NOE) FSMC_NOE low time
T_HCLK-1
T_HCLK+1
ns
t_{h(NE_NOE)} FSMC_NOE high to FSMC_NE high hold time
0
-
ns
t_{v(A_NE)} FSMC_NEx low to FSMC_A valid
-
2
ns
t_{v(NADV_NE)} FSMC_NEx low to FSMC_NADV low
1
2.5
ns
t_w(NADV) FSMC_NADV low time
T_HCLK– 1.5
T_HCLK
ns
t_{h(AD_NADV)}
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
T_HCLK
-
ns
t_{h(A_NOE)} Address hold time after FSMC_NOE high
T_HCLK
-
ns
t_{h(BL_NOE)} FSMC_BL time after FSMC_NOE high
0
-
ns
t_{v(BL_NE)} FSMC_NEx low to FSMC_BL valid
-
1
ns
t_{su(Data_NE)} Data to FSMC_NEx high setup time
T_HCLK+ 2
-
ns
t_{su(Data_NOE)} Data to FSMC_NOE high setup time
T_HCLK+ 3
-
ns
t_{h(Data_NE)} Data hold time after FSMC_NEx high
0
-
ns
t_{h(Data_NOE)} Data hold time after FSMC_NOE high
0
-
ns
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
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