CD00237391 Datasheet, PDF (22/177 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

Description
STM32F20xxx
2.2.13
2.2.14
2.2.15
2.2.16
Boot modes
At startup, boot pins are used to select one out of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
Power supply schemes
● V_DD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through V_DD pins. On WLCSP package, V_DD ranges from
1.7 to 3.6 V.
● V_SSA, V_DDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL. V_DDA and V_SSA must be connected to V_DD and V_SS, respectively.
● V_BAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and
backup registers (through power switch) when V_DD is not present.
Refer to Figure 17: Power supply scheme for more details.
Power supply supervisor
The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the
option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently. Three BOR thresholds are available through option bytes.
The device remains in reset mode when V_DD is below a specified threshold, V_POR/PDR or
V_BOR, without the need for an external reset circuit. On devices in WLCSP package, BOR
can be inactivated by setting IRROFF to V_DD (see Section 2.2.16: Voltage regulator).
The devices also feature an embedded programmable voltage detector (PVD) that monitors
the V_DD/V_DDA power supply and compares it to the V_PVD threshold. An interrupt can be
generated when V_DD/V_DDA drops below the V_PVD threshold and/or when V_DD/V_DDA is higher
than the V_PVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has five operating modes:
● Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
● Regulator OFF
– Regulator OFF/internal reset ON
– Regulator OFF/internal reset OFF
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Doc ID 15818 Rev 9